On June 20, IT Home quoted Nikkei Asia as saying that TSMC is studying a new advanced chip packaging method that uses rectangular substrates instead of traditional round wafers to place more chips on each wafer.
Sources revealed that the rectangular substrate is currently being tested and measures 510 mm by 515 mm. The available area is more than three times that of a round wafer. The use of a rectangle means that there will be less unused area left at the edge.
The report said that this research is still in its early stages, and coating photoresist in cutting-edge chip packaging on new-shaped substrates is one of the bottlenecks. Chip manufacturers with deep financial resources like TSMC are needed to push equipment manufacturers to change equipment design.
In chip manufacturing, chip packaging technology was once considered to be low-tech, but it has become increasingly important in maintaining the pace of semiconductor progress. For AI computing chips like Nvidia H200 or B200, it is not enough to just use the most advanced chip production technology.
Taking the B200 chipset as an example, TSMC's pioneering advanced chip packaging technology CoWoS can combine two Blackwell graphics processing units and connect them with eight high-bandwidth memories (HBMs) to achieve fast data throughput and accelerated computing performance.
TSMC's advanced chip stacking and assembly technology for producing AI chips for Nvidia, AMD, Amazon and Google uses 12-inch silicon wafers, the largest wafers currently available. As chip sizes increase, 12-inch wafers are gradually becoming insufficient.
Sources said that only 16 sets of B200 can be manufactured on a 12-inch wafer, and this is when the production yield is 100%. According to Morgan Stanley's estimates, the earlier H200 and H100 chips can be packaged on a wafer. About 29 sets.
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